The invention relates to unity gain amplifiers of the type commonly referred to as diamond followers, and more particularly to improvements that provide the combination of improved input offset voltage, high slew rate, and high bandwidth.
U.S. Pat. No. 4,639,685 (Saller et al.) issued Jan. 27, 1987 discloses improvements in a standard diamond follower circuit to overcome the input offset problem of the basic diamond follower circuit, which is shown in FIG. 1 of the Saller et al. patent.
FIG. 1 of the present patent application shows the circuit in FIG. 4 of the Saller et al. reference. Saller et al.'s contribution in developing that circuit is the recognition that the input offset voltage V.sub.IN -V.sub.OUT can be made equal to zero by providing two upward level shifts equal to the V.sub.BE voltages of a PNP diode-connected transistor and an NPN diode-connected transistor and also providing two downward level shifts equal to the V.sub.BE voltages of a PNP diode-connected transistor and an NPN diode-connected transistor in each of the two signal paths from V.sub.IN to V.sub.OUT. In FIG. 1, the offset voltage is equal to the V.sub.BE voltage of PNP input transistor 3 plus the V.sub.BE voltage of NPN transistor 7 minus the V.sub.BE voltage of PNP transistor 9 minus the V.sub.BE voltage of NPN output transistor 11. This offset voltage is equal to zero because the V.sub.BE voltages of PNP transistors 3 and 9 are equal and the V.sub.BE voltages of NPN transistors 7 and 11 are equal, assuming that the transistor geometries and current densities are properly matched. The offset voltage in the circuit of FIG. 1 also is equal to the sum of the V.sub.BE voltages of NPN transistor 4 and PNP transistor 16 minus the sum of the V.sub.BE voltages of NPN transistor 17 and PNP transistor 19.
A major problem with the input-offset-compensated circuit of FIG. 1 is that its slew rate is very poor because when the input transistor 3 is switched off by a fast rising transition of V.sub.IN, the constant current source 24A must charge up substantial parasitic capacitances C1 and C3, causing considerable delay in the response of V.sub.OUT. Similarly, if input transistor 4 is switched off by a rapidly falling transition of V.sub.IN, constant current source 31A must discharge substantial parasitic capacitances C2 and C4, resulting in considerable delay of the corresponding negative going downward transition of V.sub.OUT. The sloped leading and trailing edges of V.sub.OUT curve 36A in FIG. 1 indicates a poor slew rate that the circuit would have in response to a V.sub.IN pulse 35 applied to input conductor 2 (in contrast to the steep slopes of the leading and trailing edges of waveform 36 in FIG. 2, which indicates high slew rate and high bandwidth achieved by the improvement of the present invention).
U.S. Pat. No. 4,833,424 by Wright discloses a unity gain linear amplifier circuit in which current mirror circuitry boosts current to nodes of circuity which drives complementary output transistors. That circuitry is more complex than desirable, and provides considerably less "voltage head room" (i.e., room for output voltage swings) on the bases of the output transistors than is desirable.
There is a substantial unmet need for an input-offset-compensated diamond follower unity gain amplifier circuit having a high slew rate and wide bandwidth.